The present invention relates to an electrically erasable and programmable semiconductor memory device, and to a method of fabricating such a device.
Non-volatile reprogrammable semiconductor memory devices are well known in the art. See, for example, U.S. Pat. No. 4,203,158. As shown in the ""158 patent, this type of device utilizes charge tunneling between a floating gate and the silicon substrate through a dielectric to program and erase the device. This type of device requires two transistors, a floating gate transistor and a select transistor for each storage site. In this type of memory device, the ability to reduce the cell size can be limited by need to accommodate two transistors per memory cell.
Another type of semiconductor memory device is shown in U.S. Pat. Nos. 5,029,130; 5,045,488; 5,067,108; 5,242,848; and 5,278,087. These patents disclose a structure for a single transistor programmable and erasable memory cell. This structure is often referred to as a split gate cell. This transistor is formed in a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source and drain regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions disposed in the substrate. An electrically conductive floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the source to maximize capacitive coupling between the floating gate and the source. As will be discussed in more detail below, the fact that floating gate is designed to extend over a portion of the source region can operate to restrict the degree to which the cell size can be reduced.
FIG. 1 shows a cross sectional view of a split gate cell memory device of the prior art. Details of the operation and manufacturing of the split gate cell are provided in U.S. Pat. Nos. 5,029,130; 5,045,488; 5,067,108; 5,242,848; and 5,278,087. These patents are incorporated herein by reference.
The split gate cell 100 includes a substrate 120, which can be a P-type silicon substrate. A source region 116 is implanted with ions to be N type. A drain region 114 is implanted with ions to be N type. A channel region 122 is created between the source and the drain. An insulating layer 118 is disposed over the substrate, channel, source and drain. A floating gate, which is composed of a conductive material such as polysilicon, 104 is disposed over the insulating layer 118, such that it is above a portion of the channel 122 and a portion of the source 116. A second insulating layer 110 is disposed adjacent to the floating gate. The second insulating layer has a first portion 112 disposed above the floating gate 104, and second portion 108 disposed adjacent to the floating gate. The control gate 102 is disposed over and adjacent to the floating gate 104, and a portion of the control gate 106 is disposed over a portion of the channel 122. As discussed in the above referenced patents, the floating gate can be formed using a LOCOS field oxidation process, to shape the floating gate so that it has a tip pointing upward toward the control gate. This tip is used to promote efficient tunneling of electrons from the floating gate to the control gate by enhancing the effective electric field on the tip of the floating gate.
As described in the above referenced patents, the cell 100 operates such that when particular voltage differences are applied to the source, drain and control gate, electrons emanating from the drain region are injected on to the floating gate 104, as a result of an abrupt potential drop, to program the device. Further, a different range of voltages can be applied to the device, such that charge travels from the floating gate to the control gate 102 via Fowler-Nordhiem tunneling to erase the device.
Another type of semiconductor memory device is referred to a stacked gate device. Details regarding the stacked gate device are disclosed in Technical Comparison of Floating Gate Reprogrammable Nonvolatile Memories, Technical Paperfrom Silicon Storage Technologies, Revised March 1999, which is incorporated by reference. In the stacked gate device, the control gate is placed on the top of the floating gate. This configuration can offer an advantage over the split gate cell, because it occupies less space. While the stacked gate device can offer some size reduction advantages over the split gate device, in some aspects of operation, the stacked gate cell is significantly less efficient than the split gate cell. For example, typically, a significant source/drain current is required to program this device, in the range of 1 ma in a standard stacked gate device; as compared with a current of 1 xcexca in a typical split gate device.
What is needed is a device, and a method for creating a device that has a floating gate, which is shaped to provide for efficient operation, but still provides a configuration which allows for space savings similar to the stacked cell configuration.
The present invention is directed to a memory cell and a method of making a memory cell that provides for efficient operation, but also allows for the size of the device to be reduced. The method of producing such a memory cell includes the steps of forming a trench in a substrate and covering the surface of the trench with an insulating material. This insulating material is covered with a layer of conductive material, which is then etched to define a floating gate positioned above the bottom of the trench and horizontally aligned with the sidewall of the trench. The floating gate is covered with a second layer of insulating material, and a control gate is formed over the second layer of insulating material. Source and drain regions are disposed in the substrate. The source region is adjacent to a sidewall of the trench, and the drain region is positioned under the bottom of the trench.
The memory cell of the invention is formed in a substrate of semiconductor material. A trench having a sidewall and bottom is disposed in the substrate. A source region is disposed in the substrate adjacent to the sidewall of the trench. This source region is capacitively coupled with a floating gate which is positioned above the bottom of the trench and adjacent to the side wall. The source and drain regions are of a different conductivity type than the substrate. By creating an area of capacitive coupling between the source and the floating gate which is vertically, rather than horizontally, oriented relative to the substrate surface, the horizontal dimension of the memory cell device of the present invention can be reduced relative to the horizontal dimension of a prior art split cell memory device.
The features and advantages of the present invention will be more fully appreciated upon consideration of the following detailed description of the invention and the accompanying drawings, which set forth an illustrative embodiment in which the principles of the invention are utilized.